1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) device and method of manufacturing the same. More particularly, the present invention relates to a dynamic random access memory (DRAM) device and method of manufacturing the same, which can prevent problems associated with an increase in depth of metal contacts in forming thereof.
2. Description of the Related Art
As the elements incorporated into a semiconductor device are integrated to a higher degree, various attempts to form a plurality of wires or the elements in a small or narrow area in a substrate have been made. It is typical of these attempts to have the semiconductor device to become more multi-layered. Particularly, a method of forming capacitors on bit line (COB) to increase surface area thereof is widely used. In this method, metal oxide semiconductor (MOS) transistors are formed on the substrate and the capacitors connected with drains of the MOS transistors are disposed on the bit lines which supply data signals to sources of the MOS transistors. Thus, required plane area in the method can be reduced as compared with a structure having capacitors formed on the substrate.
Also, to form storage electrodes of the capacitors having a large surface area in a small substrate area, hemispherical grains (HSG) can be formed on the surface of the silicon storage electrodes. However, in this case, as the semiconductor device is highly integrated, short circuit between the adjacent storage electrodes may occur. Accordingly, in a highly integrated DRAM device, a method of adopting cylindrical shaped storage electrodes and increasing height thereof is frequently used. To increase performance of the DRAM device within the limit of a certain area, an increase in the height of the cylindrical shaped storage electrodes to several xcexcm is required. In addition, the depth of metal contacts which connect circuits within the substrate at a peripheral/core area of the DRAM device needs to be increased.
If the depth of the metal contacts is increased, according to need, silicon nitride layers have to be etched to form the metal contacts. Since it is difficult to form metal contacts having different depths in particular places, the metal contacts are prone to form short circuits with adjacent or surrounding elements. Also, since it is difficult to control the depth of the contacts, a problem may occur that the contacts are not extended enough to be connected to the required places.
FIG. 1 and FIG. 2 illustrate cross-sectional views showing portions of a cell and a peripheral/core areas of a conventional DRAM device, respectively. FIG. 1 illustrates the portion of the cell area taken parallel to gate lines and FIG. 2 illustrates problems that can occur in the peripheral/core area of the conventional DRAM device in forming of metal contacts.
Referring now to FIG. 1 and FIG. 2, an isolation layer (not shown) is formed on a semiconductor substrate 10 to define an active region. Then, a gate insulating layer is formed on the whole surface of the substrate 10 including the isolation layer by using thermal oxidation. On the gate insulating layer, a gate layer and a capping-insulating layer are formed in order. The gate layer is formed of a polysilicon layer and a metal silicide layer, whereas the capping-insulating layer is formed of a silicon nitride layer. Then, the capping-insulating layer and the conductive layer are sequentially patterned to form a gate pattern 11 including gate electrodes and wires. Thereafter, a low concentration ion implantation is carried out on the substrate 10. After spacers are formed on side walls of the gate pattern 11, a high concentration ion implantation is carried out on the substrate 10. As a result, transistors are formed to have channels and source/drain regions having dual doped structures. Over the whole surface of the substrate 10 on which the transistors are formed, a first interlayer insulating layer 15 is deposited and planarized. The first interlayer insulating layer 15 in the active region is etched to form self-aligned contact pad holes, and a conductive layer of material such as polysilicon is deposited over the substrate to fill the self-aligned contact holes. Then, the conductive layer and the first interlayer insulating layer 15 are etched by means of a chemical-mechanical planarization (CMP) process to form bit line contact pads (not shown) and storage contact pads 13 in the self-aligned contact holes.
Thereafter, a second interlayer insulating layer 17 is formed over the substrate on which the contact pads are formed. The second interlayer insulating layer 17 is patterned to form bit line contact holes 18 (not shown in the cell area of FIG. 1). At this time, in the peripheral/core area, the bit line contact holes 18 are formed at places where a bit line pattern is to be connected to the substrate, as shown in FIG. 2. Then, a barrier metal layer 19xe2x80x2 is thinly formed over the whole surface of the substrate on which the bit line contact holes are formed. Next, a conductive layer 20 of material such as tungsten is formed on the barrier metal layer 19xe2x80x2 to form bit line contacts or contact plugs. Thereafter, a barrier metal layer 19, a conductive layer 21 of material such as polysilicon, and a silicon nitride protecting layer 23 are continuously formed and patterned to form the bit line pattern, as shown in FIG. 2. Alternatively, after the bit line contact holes 18 are formed, the conductive layer 21 and the silicon nitride protecting layer 23 can be continuously formed without forming of the barrier metal layer 19xe2x80x2 and the conductive layer 20, and patterned to form the bit line pattern and the bit line contacts. On side walls of the bit line pattern, bit line spacers 25 which are composed of a silicon nitride layer are formed. The protecting layer 23 and the bit line spacers 25 function to prevent bridges between storage contact plugs and bit lines from being occurred when the storage contact plugs are formed. Thus, the bit lines having the spacers are formed. At this time, the portions of the bit line pattern having enlarged widths as described above forms bit lines having enlarged width portions at a portion of the peripheral/core area, to connect the bit lines with upper layered circuit wiring through metal contact plugs which are to be formed later.
Once the bit lines having the spacers are formed, a third interlayer insulating layer 27 is formed over the whole surface of the substrate and a planarization process is carried out to the third interlayer insulating layer 27. On the third interlayer insulating layer 27, a silicon nitride layer which acts generally as an etch stop layer 29 is formed. Then, the third interlayer insulating layer 27 and the etch stop layer 29 are patterned to form storage contact holes exposing the storage contact pads 13. And then, a conductive polysilicon layer is deposited and planarized to form storage contact plugs 31 filling the storage contact holes. Thereafter, cylindrical shaped storage electrodes 33 which are connected with the contact plugs 31 are formed and a dielectric layer 35 is thinly deposited. On the dielectric layer 35, a conductive polysilicon layer is formed and patterned to form plate electrodes 37. After a fourth interlayer insulating layer 39 is formed over the whole surface of the substrate over which the plate electrodes 37 are formed, metal contact holes are formed. A conductive layer of metal material such as CVD tungsten is deposited over the whole surface of the substrate over which the metal contact holes are formed, and planarized to form metal contact plugs 41.
At this time, when the metal contact holes are formed, there is a need to expose a portion of the plate electrodes 37 or the bit lines. Also, at a portion of the peripheral/core area, the surface of the substrate has to be exposed. Namely, the depth of the metal contact plugs 41 is different according to the positions thereof, and according to the particular needs, a portion of the metal contact plugs 41 has to be passed through the protecting layer 23 and connected to the bit lines. However, if the depth of the metal contact plugs 41 is increased whenever the height of the storage electrodes 33 is increased, there is a problem that the width of the metal contact holes is proportionally increased. An increase in the depth and the width of the metal contacts or contact plugs results in a problem that the metal contact holes are not formed deep enough to expose the surface of the substrate, or that the metal contact plugs are misaligned to penetrate a layer of adjacent elements, for example a capping layer of gate electrodes of transistors, thereby causing a short circuit with the gate electrodes, as shown in FIG. 2.
Also, if the bit lines are formed of polysilicon, and a misalignment between the bit lines and the metal contact holes has occurred, then the contact holes will be formed to expose side walls of the bit lines and circumference thereof. Under this state, if a barrier metal layer forming the metal contact plug is formed in the contact holes, bad step coverage can be formed between the side walls of the bit lines and the circumference thereof, and cracks can be generated in the barrier metal layer. Also, contact resistance between the bit lines and the metal contact plugs can be increased because of the bad step coverage and the cracks, thereby deteriorating the performance of the device.
It is a feature of an embodiment of the present invention to provide an improved dynamic random access memory (DRAM) device and method of manufacturing the same, which can prevent fabrication problems related to an increase in the depth of metal contacts.
It is another feature of an embodiment of the present invention to provide an improved dynamic random access memory (DRAM) device and method of manufacturing the same, which can prevent increase of contact resistance between the bit lines and the metal contacts and short circuit between the metal contacts and adjacent or surrounding elements due to misalignment of the metal contacts.
It is still another feature of an embodiment of the present invention to provide an improved dynamic random access memory (DRAM) device and method of manufacturing the same, which can realize a high integration density.
These and other features are provided, according to the present invention, by a method of manufacturing a DRAM device and the DRAM device manufactured thereby. The method of manufacturing DRAM device comprises forming MOS transistors on a substrate; forming an interlayer insulating layer on the whole surface of the substrate on which the MOS transistors are formed; forming at least bit line contact holes in the interlayer insulating layer deposited on the whole surface of the substrate on which the MOS transistors are formed; forming a conductive layer for forming bit lines, a subsidiary silicon oxide layer, and a subsidiary silicon nitride layer over the whole surface on which the bit line contacts are formed; forming a bit line pattern having enlarged width portions at a portion of a peripheral/core area by patterning the conductive layer, the subsidiary silicon oxide layer, and the subsidiary silicon nitride layer; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of the substrate over which the bit line pattern is formed; planarizing the bit line interlayer insulating layer to expose the upper surface of the subsidiary silicon nitride layer of the bit line pattern; forming enlarged grooves exposing portions of the conductive layer of the bit line pattern forming bit lines by wet-etching the subsidiary silicon nitride layer of the bit line pattern to form grooves and then etching isotropically the subsidiary silicon oxide layer and the bit line interlayer insulating layer around the grooves; forming a silicon nitride layer over the whole surface of the substrate over which the enlarged grooves are formed; forming a silicon nitride pattern by etching anisotropically the whole surface of the silicon nitride layer to expose the bit line interlayer insulating layer, the silicon nitride pattern having silicon nitride spacers formed on side walls of the enlarged grooves positioned on the conductive layer forming the bit lines at the enlarged width portions of the bit line pattern; forming storage node contacts, storage nodes, dielectric layer and plate electrodes at a cell area; forming a wiring interlayer insulating layer on the whole surface of the substrate over which the plate electrodes are formed; forming metal contact holes exposing the upper surface of the conductive layer of the enlarged width portions of the bit line pattern, a portion of each upper surface of plate electrodes and a portion of the upper surface of the substrate; and forming plugs filling the metal contact holes by depositing a conductive layer over the whole surface of the substrate over which the metal contact holes are formed.
In the method of the present invention, forming at least bit line contact holes can include forming separately self-aligned pads for storage node contacts and bit line contacts in said cell area. Forming self-aligned pads comprises forming a first interlayer insulating layer on the whole surface of the substrate on which the MOS transistors are formed, patterning the first interlayer insulating layer to expose a portion of an active region in the cell area, forming a polysilicon layer on the whole surface of said substrate on which the portion of the active region is exposed, and planarizing the polysilicon layer and the first interlayer insulating layer up to the upper surface of the transistors to divide the pads.
Also, forming at least bit line contacts can include forming metal contact pad holes exposing a portion of the substrate in the peripheral/core area as well as the bit line contact holes exposing a portion of the bit line contact pads in the cell area by depositing a second interlayer insulating layer and an etch stop layer of silicon nitride material over the whole surface of the substrate and patterning them, after forming the pads. Metal contact pads that function to reduce depth of metal contacts are formed in the metal contact pad holes along with bit line contacts or contact plugs. At this time, alternatively, the bit line contact plugs can be formed along with the bit line pattern in the step of forming the bit line pattern. The etch stop layer can prevent a portion of the interlayer insulating layer adjacent to the metal contact pad holes from being etched and thereby formation of a bridge or short circuit between the metal contact plug to be formed later and surrounding gate lines can be prevented even though the metal contact holes for the metal contact plugs are formed to have a relatively large width or misaligned slightly. After forming of the bit line contact plugs, the etch stop layer is patterned to leave only a portion thereof around the metal contact pads.
According to the DRAM device in accordance with the present invention, the DRAM device comprises a portion of bit lines having enlarged width portions at a portion of a peripheral/core area to connect the bit lines with upper layered circuit wiring through metal contacts; and spacers formed of a layer of material having an etch selectivity with respect to a bit line interlayer insulating layer deposited after the bit lines are formed, and disposed on sides of an upper surface of each enlarged width portion to protect sides of the enlarged width portions. Preferably, an interlayer insulating layer and an etch stop layer of material having an etch selectivity with respect to the bit line interlayer insulating layer are disposed between the bit lines and transistors of a substrate, and metal contact pads formed along with bit line contact plugs are formed to pass through the interlayer insulating layer and the etch stop layer.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.